Job Description

Position : Physical Design Engineer (Einfochips Inc)

Job Description

What candidate will Be Doing:

• Netlist to-GDSII implementation, including top-level floorplanning, design partitioning, top level block to block/over the block routing, repeater flops and balance flop concepts, top level clock structure planning, clock network SPICE simulation, power mesh planning, and full signoff (DRC, LVS, STA, EMIR).
• Own and drive PnR execution and closure at both block and top levels, addressing timing, congestion, IR-drop, and physical verification challenges.
• Proficient with industry-standard tools: Synopsys ICC2, Fusion Compiler and scripting in Tcl, Perl, Python for automation and flow development.
• Expertise in clock gating, logic optimization, and integration of high-speed interfaces like DDR and PCIe.
• Collaborate cross-functionally with RTL, STA, DFT, verification, and packaging teams to ensure smooth integration and closure.
• Manage comprehensive signoff processes, including STA (PrimeTime SI), EM/IR analysis (RedHawk), and physical verification (Calibre); handle ECOs and DRC/LVS clean-up.
• Provide technical leadership, mentor junior engineers, and contribute to successful tape outs at advanced technology nodes (5nm and 3nm).

What We Are Looking For

• 10+ years of experience in Physical Design (RTL-to-GDSII flow) for complex SoCs/ASICs.
• Strong expertise in Floor Planning, including partitioning, block-level planning, and optimization.
• Hands-on experience in Place & Route (PnR) using industry-standard EDA tools.
• Solid background in Static Timing Analysis (STA) and timing closure across multiple corners and modes.
• Proven ability in DRC/LVS clean-up and sign-off checks.
• Experience in Logical Equivalence Checking (LEC) and debugging mismatches.
• Good understanding of Power analysis, EM/IR drop analysis, and power integrity methodologies.
• Strong TCL scripting skills for flow automation and EDA tool integration.

Work Arrangement : Fully Onsite. Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.

Location : San Jose, CA

Whats In It For You

At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. Thats why we offer competitive financial compensation, including various compensation plans and a solid benefits package.

• Medical, Dental, Vision Insurance
• 401k, With Matching Contributions
• Short-Term/Long-Term Disability Insurance
• Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options
• Paid Time Off (including sick, holiday, vacation, etc.)
• Tuition Reimbursement
• Growth Opportunities
• And more!

About EInfochips

eInfochips, an Arrow company (Fortune #133), is a leading global provider of product engineering and semiconductor design services.

Annual Hiring Range/Hourly Rate : $160,000 - $180,000/annum

EEO Statement : Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)

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